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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl] - Rev 55

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Rev Log message Author Age Path
55 Fixed up sdr16 dqm output julius 5345d 07h /versatile_mem_ctrl/trunk/rtl
54 dqm moved into FSM unneback 5346d 04h /versatile_mem_ctrl/trunk/rtl
53 unneback 5346d 04h /versatile_mem_ctrl/trunk/rtl
52 act exit for read updated unneback 5347d 06h /versatile_mem_ctrl/trunk/rtl
51 act exit for read updated unneback 5347d 06h /versatile_mem_ctrl/trunk/rtl
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5347d 08h /versatile_mem_ctrl/trunk/rtl
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5347d 10h /versatile_mem_ctrl/trunk/rtl
48 dq_oe fix unneback 5347d 10h /versatile_mem_ctrl/trunk/rtl
47 support for registered outputs on ras, cas and we unneback 5347d 10h /versatile_mem_ctrl/trunk/rtl
46 cosmetic updates unneback 5347d 11h /versatile_mem_ctrl/trunk/rtl
45 added unneback 5347d 14h /versatile_mem_ctrl/trunk/rtl
44 registered row comparison unneback 5349d 13h /versatile_mem_ctrl/trunk/rtl
42 added pipeline stage for egress FIFO readot unneback 5350d 03h /versatile_mem_ctrl/trunk/rtl
41 Added two alternate data capture functions. mikaeljf 5350d 10h /versatile_mem_ctrl/trunk/rtl
40 updated fifo interfaces with re/rd and we/wr unneback 5350d 17h /versatile_mem_ctrl/trunk/rtl
39 updated FIFO and SDR 16 unneback 5351d 05h /versatile_mem_ctrl/trunk/rtl
38 casex in rw state to save logic unneback 5353d 12h /versatile_mem_ctrl/trunk/rtl
37 unneback 5354d 03h /versatile_mem_ctrl/trunk/rtl
36 unneback 5354d 03h /versatile_mem_ctrl/trunk/rtl
35 work for limited test case unneback 5354d 11h /versatile_mem_ctrl/trunk/rtl

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