URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [sim/] [rtl_sim/] [bin] - Rev 82

Rev	Log message	Author	Age	Path
82		mikaeljf	5161d 11h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
80		mikaeljf	5162d 08h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
75		mikaeljf	5215d 06h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
70		mikaeljf	5222d 13h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
69		mikaeljf	5223d 10h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5249d 04h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5253d 06h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5281d 09h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5286d 05h	/versatile_mem_ctrl/trunk/sim/rtl_sim/bin