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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [bin] - Rev 86

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86 mikaeljf 5134d 07h /versatile_mem_ctrl/trunk/syn/altera/bin
84 mikaeljf 5139d 06h /versatile_mem_ctrl/trunk/syn/altera/bin
83 mikaeljf 5140d 02h /versatile_mem_ctrl/trunk/syn/altera/bin
81 mikaeljf 5141d 03h /versatile_mem_ctrl/trunk/syn/altera/bin
75 mikaeljf 5194d 01h /versatile_mem_ctrl/trunk/syn/altera/bin
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5228d 00h /versatile_mem_ctrl/trunk/syn/altera/bin
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5247d 19h /versatile_mem_ctrl/trunk/syn/altera/bin
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5251d 22h /versatile_mem_ctrl/trunk/syn/altera/bin
20 Minor update of sdc-file. mikaeljf 5253d 23h /versatile_mem_ctrl/trunk/syn/altera/bin
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5265d 01h /versatile_mem_ctrl/trunk/syn/altera/bin

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