OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 100

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
100 unneback 4899d 23h /versatile_mem_ctrl/trunk
99 updated stimuli with automatic check unneback 4899d 23h /versatile_mem_ctrl/trunk
98 updates unneback 5003d 04h /versatile_mem_ctrl/trunk
97 updated tb and sdram16 unneback 5003d 17h /versatile_mem_ctrl/trunk
96 doc update unneback 5034d 05h /versatile_mem_ctrl/trunk
95 new files unneback 5038d 18h /versatile_mem_ctrl/trunk
94 new TB unneback 5047d 01h /versatile_mem_ctrl/trunk
86 mikaeljf 5110d 06h /versatile_mem_ctrl/trunk
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5111d 06h /versatile_mem_ctrl/trunk
84 mikaeljf 5115d 05h /versatile_mem_ctrl/trunk
83 mikaeljf 5116d 00h /versatile_mem_ctrl/trunk
82 mikaeljf 5116d 05h /versatile_mem_ctrl/trunk
81 mikaeljf 5117d 01h /versatile_mem_ctrl/trunk
80 mikaeljf 5117d 02h /versatile_mem_ctrl/trunk
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5154d 16h /versatile_mem_ctrl/trunk
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5156d 23h /versatile_mem_ctrl/trunk
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5164d 21h /versatile_mem_ctrl/trunk
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5169d 22h /versatile_mem_ctrl/trunk
75 mikaeljf 5170d 00h /versatile_mem_ctrl/trunk
74 Minor update of rtl Makefile. mikaeljf 5173d 23h /versatile_mem_ctrl/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.