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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 101

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Rev Log message Author Age Path
101 cleaning up unneback 4922d 03h /versatile_mem_ctrl/trunk
100 unneback 4922d 03h /versatile_mem_ctrl/trunk
99 updated stimuli with automatic check unneback 4922d 03h /versatile_mem_ctrl/trunk
98 updates unneback 5025d 08h /versatile_mem_ctrl/trunk
97 updated tb and sdram16 unneback 5025d 21h /versatile_mem_ctrl/trunk
96 doc update unneback 5056d 09h /versatile_mem_ctrl/trunk
95 new files unneback 5060d 22h /versatile_mem_ctrl/trunk
94 new TB unneback 5069d 06h /versatile_mem_ctrl/trunk
86 mikaeljf 5132d 10h /versatile_mem_ctrl/trunk
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5133d 11h /versatile_mem_ctrl/trunk
84 mikaeljf 5137d 09h /versatile_mem_ctrl/trunk
83 mikaeljf 5138d 05h /versatile_mem_ctrl/trunk
82 mikaeljf 5138d 09h /versatile_mem_ctrl/trunk
81 mikaeljf 5139d 06h /versatile_mem_ctrl/trunk
80 mikaeljf 5139d 07h /versatile_mem_ctrl/trunk
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5176d 20h /versatile_mem_ctrl/trunk
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5179d 03h /versatile_mem_ctrl/trunk
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5187d 02h /versatile_mem_ctrl/trunk
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5192d 03h /versatile_mem_ctrl/trunk
75 mikaeljf 5192d 04h /versatile_mem_ctrl/trunk

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