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URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 12

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Rev Log message Author Age Path
12 Minor update of whishbone FSMs in TB mikaeljf 5468d 22h /versatile_mem_ctrl/trunk
11 Initial version with support for DDR mikaeljf 5469d 10h /versatile_mem_ctrl/trunk
10 unneback 5496d 18h /versatile_mem_ctrl/trunk
9 testbench unneback 5496d 18h /versatile_mem_ctrl/trunk
8 unneback 5592d 14h /versatile_mem_ctrl/trunk
7 unneback 5592d 14h /versatile_mem_ctrl/trunk
6 unneback 5592d 15h /versatile_mem_ctrl/trunk
5 pass initial testing unneback 5592d 15h /versatile_mem_ctrl/trunk
4 unneback 5593d 18h /versatile_mem_ctrl/trunk
3 unneback 5593d 21h /versatile_mem_ctrl/trunk
2 initial unneback 5599d 19h /versatile_mem_ctrl/trunk
1 The project was created and the structure was created root 5599d 19h /versatile_mem_ctrl/trunk

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