URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 14

Rev	Log message	Author	Age	Path
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5392d 19h	/versatile_mem_ctrl/trunk
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5392d 22h	/versatile_mem_ctrl/trunk
12	Minor update of whishbone FSMs in TB	mikaeljf	5402d 23h	/versatile_mem_ctrl/trunk
11	Initial version with support for DDR	mikaeljf	5403d 11h	/versatile_mem_ctrl/trunk
10		unneback	5430d 18h	/versatile_mem_ctrl/trunk
9	testbench	unneback	5430d 19h	/versatile_mem_ctrl/trunk
8		unneback	5526d 15h	/versatile_mem_ctrl/trunk
7		unneback	5526d 15h	/versatile_mem_ctrl/trunk
6		unneback	5526d 15h	/versatile_mem_ctrl/trunk
5	pass initial testing	unneback	5526d 15h	/versatile_mem_ctrl/trunk
4		unneback	5527d 18h	/versatile_mem_ctrl/trunk
3		unneback	5527d 21h	/versatile_mem_ctrl/trunk
2	initial	unneback	5533d 19h	/versatile_mem_ctrl/trunk
1	The project was created and the structure was created	root	5533d 19h	/versatile_mem_ctrl/trunk