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[/] [versatile_mem_ctrl/] [trunk] - Rev 40

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Rev Log message Author Age Path
40 updated fifo interfaces with re/rd and we/wr unneback 5322d 20h /versatile_mem_ctrl/trunk
39 updated FIFO and SDR 16 unneback 5323d 08h /versatile_mem_ctrl/trunk
38 casex in rw state to save logic unneback 5325d 15h /versatile_mem_ctrl/trunk
37 unneback 5326d 06h /versatile_mem_ctrl/trunk
36 unneback 5326d 06h /versatile_mem_ctrl/trunk
35 work for limited test case unneback 5326d 14h /versatile_mem_ctrl/trunk
34 added unneback 5326d 14h /versatile_mem_ctrl/trunk
33 work for limited test case, no cke inhibit for fifo empty unneback 5326d 16h /versatile_mem_ctrl/trunk
32 Updated the testbench to match the new wishbone interface. mikaeljf 5329d 20h /versatile_mem_ctrl/trunk
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5331d 13h /versatile_mem_ctrl/trunk
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5331d 13h /versatile_mem_ctrl/trunk
29 Adapted the test bench to the new wishbone interface. mikaeljf 5335d 13h /versatile_mem_ctrl/trunk
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5335d 15h /versatile_mem_ctrl/trunk
27 unneback 5339d 07h /versatile_mem_ctrl/trunk
26 compiles OK, not simulated unneback 5341d 06h /versatile_mem_ctrl/trunk
25 unneback 5341d 08h /versatile_mem_ctrl/trunk
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5341d 20h /versatile_mem_ctrl/trunk
23 Removed redundant code. mikaeljf 5349d 12h /versatile_mem_ctrl/trunk
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5351d 08h /versatile_mem_ctrl/trunk
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5355d 11h /versatile_mem_ctrl/trunk

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