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[/] [versatile_mem_ctrl] - Rev 23

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23 Removed redundant code. mikaeljf 5318d 02h /versatile_mem_ctrl
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5319d 21h /versatile_mem_ctrl
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5324d 01h /versatile_mem_ctrl
20 Minor update of sdc-file. mikaeljf 5326d 02h /versatile_mem_ctrl
19 Added do-file for Modelsim waveform viewer. mikaeljf 5332d 07h /versatile_mem_ctrl
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5333d 04h /versatile_mem_ctrl
17 Modified rtl Makefile and tb_defines.v mikaeljf 5336d 03h /versatile_mem_ctrl
16 Added fizzim.pl mikaeljf 5336d 03h /versatile_mem_ctrl
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5337d 03h /versatile_mem_ctrl
14 Added external feedback of DDR SDRAM clock. mikaeljf 5427d 06h /versatile_mem_ctrl
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5427d 08h /versatile_mem_ctrl
12 Minor update of whishbone FSMs in TB mikaeljf 5437d 09h /versatile_mem_ctrl
11 Initial version with support for DDR mikaeljf 5437d 21h /versatile_mem_ctrl
10 unneback 5465d 05h /versatile_mem_ctrl
9 testbench unneback 5465d 05h /versatile_mem_ctrl
8 unneback 5561d 01h /versatile_mem_ctrl
7 unneback 5561d 01h /versatile_mem_ctrl
6 unneback 5561d 01h /versatile_mem_ctrl
5 pass initial testing unneback 5561d 02h /versatile_mem_ctrl
4 unneback 5562d 05h /versatile_mem_ctrl

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