OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 42

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
42 added pipeline stage for egress FIFO readot unneback 5227d 05h /versatile_mem_ctrl
41 Added two alternate data capture functions. mikaeljf 5227d 13h /versatile_mem_ctrl
40 updated fifo interfaces with re/rd and we/wr unneback 5227d 20h /versatile_mem_ctrl
39 updated FIFO and SDR 16 unneback 5228d 08h /versatile_mem_ctrl
38 casex in rw state to save logic unneback 5230d 15h /versatile_mem_ctrl
37 unneback 5231d 06h /versatile_mem_ctrl
36 unneback 5231d 06h /versatile_mem_ctrl
35 work for limited test case unneback 5231d 13h /versatile_mem_ctrl
34 added unneback 5231d 14h /versatile_mem_ctrl
33 work for limited test case, no cke inhibit for fifo empty unneback 5231d 16h /versatile_mem_ctrl
32 Updated the testbench to match the new wishbone interface. mikaeljf 5234d 20h /versatile_mem_ctrl
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 13h /versatile_mem_ctrl
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 13h /versatile_mem_ctrl
29 Adapted the test bench to the new wishbone interface. mikaeljf 5240d 13h /versatile_mem_ctrl
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5240d 15h /versatile_mem_ctrl
27 unneback 5244d 07h /versatile_mem_ctrl
26 compiles OK, not simulated unneback 5246d 06h /versatile_mem_ctrl
25 unneback 5246d 08h /versatile_mem_ctrl
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5246d 20h /versatile_mem_ctrl
23 Removed redundant code. mikaeljf 5254d 12h /versatile_mem_ctrl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.