URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 46

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Rev	Log message	Author	Age	Path
46	cosmetic updates	unneback	5224d 15h	/versatile_mem_ctrl
45	added	unneback	5224d 17h	/versatile_mem_ctrl
44	registered row comparison	unneback	5226d 17h	/versatile_mem_ctrl
43		unneback	5226d 22h	/versatile_mem_ctrl
42	added pipeline stage for egress FIFO readot	unneback	5227d 06h	/versatile_mem_ctrl
41	Added two alternate data capture functions.	mikaeljf	5227d 14h	/versatile_mem_ctrl
40	updated fifo interfaces with re/rd and we/wr	unneback	5227d 21h	/versatile_mem_ctrl
39	updated FIFO and SDR 16	unneback	5228d 08h	/versatile_mem_ctrl
38	casex in rw state to save logic	unneback	5230d 16h	/versatile_mem_ctrl
37		unneback	5231d 06h	/versatile_mem_ctrl
36		unneback	5231d 07h	/versatile_mem_ctrl
35	work for limited test case	unneback	5231d 14h	/versatile_mem_ctrl
34	added	unneback	5231d 14h	/versatile_mem_ctrl
33	work for limited test case, no cke inhibit for fifo empty	unneback	5231d 17h	/versatile_mem_ctrl
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5234d 21h	/versatile_mem_ctrl
31	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5236d 14h	/versatile_mem_ctrl
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5236d 14h	/versatile_mem_ctrl
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5240d 14h	/versatile_mem_ctrl
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5240d 16h	/versatile_mem_ctrl
27		unneback	5244d 07h	/versatile_mem_ctrl

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 46

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