URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [tags/] [rel_19/] [bench/] [verilog/] [sync_check.v] - Rev 60

Rev	Log message	Author	Age	Path
60	all WB outputs are registered, but just when we dont use cursors	markom	7656d 02h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
52	Numerous updates and added checks	rherveille	7795d 05h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7844d 03h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8333d 08h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8419d 09h	/vga_lcd/tags/rel_19/bench/verilog/sync_check.v