URL https://opencores.org/ocsvn/vga_lcd/vga_lcd/trunk

Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk/] [bench/] [verilog/] [test_bench_top.v] - Rev 62

Rev	Log message	Author	Age	Path
62	New directory structure.	root	5697d 08h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
60	all WB outputs are registered, but just when we dont use cursors	markom	7692d 05h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
58	Enabled Fifo Underrun test	rherveille	7724d 11h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
54	Added DVI tests	rherveille	7831d 04h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
52	Numerous updates and added checks	rherveille	7831d 09h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
46	Added WISHBONE revB.3 sanity checks	rherveille	7880d 01h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
44	Changed timing section in VGA core, changed testbench accordingly. Fixed bug in 'timing check' test.	rherveille	7880d 06h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
29	Added wb_ack delay section to testbench	rherveille	8285d 13h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
26	Added 32bpp tests	rherveille	8295d 15h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
24	Updated testbench for VGA/LCD Core version 2.0	rherveille	8369d 11h	/vga_lcd/trunk/bench/verilog/test_bench_top.v
16	- Changed Directory Structure - Added verilog Source Code - Changed IO pin names and defines statements	rudi	8455d 13h	/vga_lcd/trunk/bench/verilog/test_bench_top.v