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Subversion Repositories vga_lcd

[/] [vga_lcd/] [trunk] - Rev 62

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Rev Log message Author Age Path
62 New directory structure. root 5562d 05h /vga_lcd/trunk
60 all WB outputs are registered, but just when we dont use cursors markom 7557d 02h /trunk
59 Removed ctrl register's clut and vide bank switch from the register test. As they get reset automatically. This may result to erroneous errors. rherveille 7589d 08h /trunk
58 Enabled Fifo Underrun test rherveille 7589d 08h /trunk
57 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
2) Changed top level and pixel generator to reflect changes in the fifo.
3) Changed a bug in vga_fifo.
4) Changed pixel generator and wishbone master to reflect changes.		 rherveille 7610d 03h /trunk
56 Removed 'or negedge arst' from sluint/luint sensitivity list rherveille 7639d 00h /trunk
55 Initial release. rherveille 7696d 00h /trunk
54 Added DVI tests rherveille 7696d 00h /trunk
53 Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.		 rherveille 7696d 05h /trunk
52 Numerous updates and added checks rherveille 7696d 05h /trunk
51 Forgot to change document revision number rherveille 7744d 00h /trunk
50 Forgot to change document revision rherveille 7744d 00h /trunk
49 Added WISHBONE revB.3 signals rherveille 7744d 01h /trunk
48 WISHBONE revB.3 signals added rherveille 7744d 01h /trunk
47 Added wb_b3_check
Removed ud_cnt, ro_cnt		 rherveille 7744d 22h /trunk
46 Added WISHBONE revB.3 sanity checks rherveille 7744d 22h /trunk
45 Changed timing generator; made it smaller and easier. rherveille 7745d 02h /trunk
44 Changed timing section in VGA core, changed testbench accordingly.
Fixed bug in 'timing check' test.		 rherveille 7745d 03h /trunk
43 Added WISHBONE revB.3 Registered Feedback Cycles support rherveille 7745d 17h /trunk
41 specs version 1.1 rherveille 8078d 04h /trunk

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