URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] [trunk] - Rev 25

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Rev	Log message	Author	Age	Path
25	Added scripts and constraints for KCU105	fransschreuder	3245d 12h	/virtex7_pcie_dma/trunk
24	Added: * Support for KCU105 board in code TODO * Add constraints and build scripts for KCU105	fransschreuder	3246d 06h	/virtex7_pcie_dma/trunk
23	Fixed reset of application registers	fransschreuder	3303d 11h	/virtex7_pcie_dma/trunk
22	Added dma_soft_reset to trigger register resets	fransschreuder	3309d 11h	/virtex7_pcie_dma/trunk
21	Fixed BUG http://opencores.org/bug,view,2562	fransschreuder	3318d 08h	/virtex7_pcie_dma/trunk
20	Fixed: * Missing packets if the fifo goes empty during a TLP * Dynamically change the empty threshold of the main fifo to TLP size	fransschreuder	3332d 07h	/virtex7_pcie_dma/trunk
19	* driver/README updated	oussamak	3338d 09h	/virtex7_pcie_dma/trunk
18	Changed: * Added drivers * Added Wupper tools for debugging * Added card ID register	oussamak	3338d 11h	/virtex7_pcie_dma/trunk
17	Changed name of toplevel, to make tree consistent	oussamak	3352d 13h	/virtex7_pcie_dma/trunk
16	MODIFED: -- top level name to wupper_oc (including scripts)	aborga	3402d 07h	/virtex7_pcie_dma/trunk
15	MODIFIED: -- Renamed core to Wupper (vhdl files) -- Changed width of interrupt enable to number_of_interrupts	fransschreuder	3402d 07h	/virtex7_pcie_dma/trunk
14	RENAMED: -- simulation folder	aborga	3402d 09h	/virtex7_pcie_dma/trunk
13	RENAMED: -- script	aborga	3402d 09h	/virtex7_pcie_dma/trunk
12	Fixed http://opencores.org/bug,view,2524	fransschreuder	3477d 09h	/virtex7_pcie_dma/trunk
11	MODIFIED: -- updated documentation	aborga	3490d 06h	/virtex7_pcie_dma/trunk
10	Changed: LOC => Package_pin	fransschreuder	3500d 07h	/virtex7_pcie_dma/trunk
9	Added actual version information (Build date and svn revision) in BOARD_ID register	fransschreuder	3529d 05h	/virtex7_pcie_dma/trunk
8	Changed: * Added support for circular DMA (wrap around) * Fixed Read / Write interrupts	fransschreuder	3529d 11h	/virtex7_pcie_dma/trunk
7	Changed: * Simplified address calculation to relax timing * Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing * Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk * Added support for the High tech Global HTG710 board	fransschreuder	3569d 07h	/virtex7_pcie_dma/trunk
6	Changed: * fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable * Fixed missing signals in sensitivity list	fransschreuder	3575d 05h	/virtex7_pcie_dma/trunk

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Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] [trunk] - Rev 25

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