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[/] [vspi] - Rev 14

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Rev Log message Author Age Path
14 Merge branch 'master' into svn mjlyons 4494d 16h /vspi
13 Starting over, again mjlyons 4494d 17h /vspi
12 Merge branch 'master' into svn mjlyons 4494d 17h /vspi
11 Starting over mjlyons 4494d 20h /vspi
10 Correctly read single-byte incoming transmissions (PC->FPGA). mjlyons 4494d 21h /vspi
9 Checking in in-progress SPI. Need to move command decode to SPI clock rather than sysclk. mjlyons 4494d 21h /vspi
8 SPI Test python script now includes test for receiving a 1KB block from FPGA mjlyons 4494d 22h /vspi
7 Updating master scripts (cheetah) to test new vSPI receive functionality mjlyons 4494d 22h /vspi
6 Now support receiving data (Cheetah->vSPI) mjlyons 4494d 22h /vspi
5 Adding script to control cheetah spi adapter and test vSPI mjlyons 4494d 22h /vspi
4 Correctly read single-byte incoming transmissions (PC->FPGA). mjlyons 4494d 22h /vspi
3 Checking in in-progress SPI. Need to move command decode to SPI clock rather than sysclk. mjlyons 4494d 22h /vspi
2 first commit mjlyons 4494d 22h /vspi
1 The project and the structure was created root 4495d 11h /vspi

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