URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl/] [wbm2axisp.v] - Rev 16

Rev	Log message	Author	Age	Path
16	Lots of updates (see below) New files: 1. AXI-lite formal checker(s) 2. AXI-lite to WB bridge 3. WB to AXI-lite bridge 4. WB cross bar (for lack of a better place) 5. Demonstration/example AXI-lite core Other files have been updated as necessary. Ex. the WB formal checker files.	dgisselq	2100d 08h	/wb2axip/trunk/rtl/wbm2axisp.v
15	Quick update, making this module verilatable again	dgisselq	2460d 11h	/wb2axip/trunk/rtl/wbm2axisp.v
14	Added a reset line upon user request	dgisselq	2460d 11h	/wb2axip/trunk/rtl/wbm2axisp.v
13	Bug fix release--fixes the bugs Antti pointed out.	dgisselq	2473d 01h	/wb2axip/trunk/rtl/wbm2axisp.v
8	The WB to AXI translator wrks and works well. A proof of this will be added shortly.	dgisselq	2570d 12h	/wb2axip/trunk/rtl/wbm2axisp.v
6	IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet)	dgisselq	3015d 08h	/wb2axip/trunk/rtl/wbm2axisp.v
5	Adjusted variable names to match the spec and the MIG.	dgisselq	3019d 23h	/wb2axip/trunk/rtl/wbm2axisp.v
4	Adjusted the core quickly so it should work for 128-bit wide wishbone busses as well as 32-bit wide busses.	dgisselq	3020d 05h	/wb2axip/trunk/rtl/wbm2axisp.v
3	Fixed the Verilator compile-time bugs. Still haven't tested the core.	dgisselq	3020d 05h	/wb2axip/trunk/rtl/wbm2axisp.v
2	Initial check in. Core not (yet) tested, verified, or validated.	dgisselq	3020d 06h	/wb2axip/trunk/rtl/wbm2axisp.v