URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] [trunk/] [rtl/] [wbm2axisp.v] - Rev 15

Rev	Log message	Author	Age	Path
15	Quick update, making this module verilatable again	dgisselq	2261d 20h	/wb2axip/trunk/rtl/wbm2axisp.v
14	Added a reset line upon user request	dgisselq	2261d 20h	/wb2axip/trunk/rtl/wbm2axisp.v
13	Bug fix release--fixes the bugs Antti pointed out.	dgisselq	2274d 09h	/wb2axip/trunk/rtl/wbm2axisp.v
8	The WB to AXI translator wrks and works well. A proof of this will be added shortly.	dgisselq	2371d 21h	/wb2axip/trunk/rtl/wbm2axisp.v
6	IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet)	dgisselq	2816d 17h	/wb2axip/trunk/rtl/wbm2axisp.v
5	Adjusted variable names to match the spec and the MIG.	dgisselq	2821d 08h	/wb2axip/trunk/rtl/wbm2axisp.v
4	Adjusted the core quickly so it should work for 128-bit wide wishbone busses as well as 32-bit wide busses.	dgisselq	2821d 13h	/wb2axip/trunk/rtl/wbm2axisp.v
3	Fixed the Verilator compile-time bugs. Still haven't tested the core.	dgisselq	2821d 14h	/wb2axip/trunk/rtl/wbm2axisp.v
2	Initial check in. Core not (yet) tested, verified, or validated.	dgisselq	2821d 14h	/wb2axip/trunk/rtl/wbm2axisp.v