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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_pri_enc_sub.v] - Rev 15

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15 - Minor cleanup rudi 8198d 01h /wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v
10 - Made the core parameterized rudi 8302d 23h /wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v
8 - Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
- Added Section 3.10, describing DMA restart.
rudi 8367d 22h /wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v
6 Split up priority encoder modules to separate files rudi 8375d 19h /wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v

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