URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdram_tb.cpp] - Rev 12

Rev	Log message	Author	Age	Path
12	Added the write-read and write-precharge extra delays into both module and simulation.	dgisselq	2861d 21h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
10	This might just work ... at least, it passes my testbench.	dgisselq	2861d 23h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
9	Making progress: The singular write and pipe read tests work. Random pipe reads still failing.	dgisselq	2861d 23h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	2862d 08h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	2863d 17h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	2864d 17h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	2865d 15h	/wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp