URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [doc] - Rev 18

Rev	Log message	Author	Age	Path
18	We now pass all tests again--this time for a 4:1 controller, with a CAS of 5 and a CWL of 5. This is designed for a memory running at 320MHz, transmitting across the data lines as 640Mbps, and yet running internally at only 80MHz.	dgisselq	2942d 00h	/wbddr3/trunk/doc
15	Some simple timing diagrams, illustrating how we can go about this.	dgisselq	2973d 11h	/wbddr3/trunk/doc
13	Cleanup, bug fixes--sadly, the code no longer works, so while it's "better" in that it can build at 200MHz, it no longer works in the Verilator simulation.	dgisselq	2987d 01h	/wbddr3/trunk/doc
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	2988d 16h	/wbddr3/trunk/doc
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	2992d 16h	/wbddr3/trunk/doc