URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [rtl/] [wbddrsdram.v] - Rev 9

Rev	Log message	Author	Age	Path
9	Making progress: The singular write and pipe read tests work. Random pipe reads still failing.	dgisselq	2861d 14h	/wbddr3/trunk/rtl/wbddrsdram.v
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	2861d 23h	/wbddr3/trunk/rtl/wbddrsdram.v
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	2863d 08h	/wbddr3/trunk/rtl/wbddrsdram.v
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	2864d 08h	/wbddr3/trunk/rtl/wbddrsdram.v
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	2864d 15h	/wbddr3/trunk/rtl/wbddrsdram.v
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	2865d 06h	/wbddr3/trunk/rtl/wbddrsdram.v
3	Fixes some, not all, of the Verilator build/lint errors.	dgisselq	2865d 22h	/wbddr3/trunk/rtl/wbddrsdram.v
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	2865d 23h	/wbddr3/trunk/rtl/wbddrsdram.v