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URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk] - Rev 14

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Rev	Log message	Author	Age	Path
14	Lots of changes. Redesigned the refresh logic, and the activate/precharge logic. While it's still not working on the hardware, it looks better than before. (I also caught some bugs in the MRx register settings ...)	dgisselq	2880d 00h	/wbddr3/trunk
13	Cleanup, bug fixes--sadly, the code no longer works, so while it's "better" in that it can build at 200MHz, it no longer works in the Verilator simulation.	dgisselq	2880d 23h	/wbddr3/trunk
12	Added the write-read and write-precharge extra delays into both module and simulation.	dgisselq	2882d 04h	/wbddr3/trunk
11	Fixed the bugs Xilinx's tools pointed out.	dgisselq	2882d 05h	/wbddr3/trunk
10	This might just work ... at least, it passes my testbench.	dgisselq	2882d 06h	/wbddr3/trunk
9	Making progress: The singular write and pipe read tests work. Random pipe reads still failing.	dgisselq	2882d 06h	/wbddr3/trunk
8	Singular reads and writes now work (in the Verilator simulator)--just not pipelined reads or writes.	dgisselq	2882d 15h	/wbddr3/trunk
7	Make lots of progress. Reset works, and refresh is within a clock measurement or two of working properly. Singular sequential writes work as well.	dgisselq	2884d 00h	/wbddr3/trunk
6	Lots of bug fixes. The controller now proceeds through the proper reset logic into the first write. This includes activating the needed bank and the next one, and then issuing the write command. It doesn't complete the write command yet, but that's the next step.	dgisselq	2885d 00h	/wbddr3/trunk
5	Under Verilator/simulation testing, the core now properly brings the device up from reset. Next step: opening/closing banks.	dgisselq	2885d 06h	/wbddr3/trunk
4	Work continues. A preliminary test-bench has been created. The core has yet to pass through the reset cycle yet, so there's a lot of work still to be done.	dgisselq	2885d 22h	/wbddr3/trunk
3	Fixes some, not all, of the Verilator build/lint errors.	dgisselq	2886d 13h	/wbddr3/trunk
2	Initial checkin. Pieces are not working yet, but the general approach is starting to take shape.	dgisselq	2886d 15h	/wbddr3/trunk
1	The project and the structure was created	root	2886d 19h	/wbddr3/trunk

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