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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 100

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Rev Log message Author Age Path
100 Enabled PC underflow test. rehayes 4318d 19h /xgate/trunk/bench/verilog/tst_bench_top.v
94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4729d 11h /xgate/trunk/bench/verilog/tst_bench_top.v
89 Code cleanup. rehayes 4743d 10h /xgate/trunk/bench/verilog/tst_bench_top.v
86 Add JTAG test tasks rehayes 4943d 09h /xgate/trunk/bench/verilog/tst_bench_top.v
82 Added debug module to assist in software debugging. rehayes 5218d 13h /xgate/trunk/bench/verilog/tst_bench_top.v
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5308d 17h /xgate/trunk/bench/verilog/tst_bench_top.v
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5309d 20h /xgate/trunk/bench/verilog/tst_bench_top.v
65 Parameterize delays based on number of RAM wait states. rehayes 5329d 16h /xgate/trunk/bench/verilog/tst_bench_top.v
62 Cleanup implicit wire declarations. rehayes 5339d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
60 Add ability at insert wait states on RAM access rehayes 5346d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5414d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
50 incremental update to match status bit changes rehayes 5430d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5465d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5493d 20h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5526d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5540d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5553d 15h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5561d 13h /xgate/trunk/bench/verilog/tst_bench_top.v

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