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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 50

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Rev Log message Author Age Path
50 incremental update to match status bit changes rehayes 5294d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5329d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5357d 22h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5390d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5404d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5417d 18h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5425d 16h /xgate/trunk/bench/verilog/tst_bench_top.v

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