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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 68

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68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5159d 05h /xgate/trunk/bench/verilog/tst_bench_top.v
65 Parameterize delays based on number of RAM wait states. rehayes 5179d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
62 Cleanup implicit wire declarations. rehayes 5189d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
60 Add ability at insert wait states on RAM access rehayes 5196d 00h /xgate/trunk/bench/verilog/tst_bench_top.v
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5264d 04h /xgate/trunk/bench/verilog/tst_bench_top.v
50 incremental update to match status bit changes rehayes 5280d 00h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5315d 00h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5343d 05h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5376d 00h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5390d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5403d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5410d 22h /xgate/trunk/bench/verilog/tst_bench_top.v

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