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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 86

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86 Add JTAG test tasks rehayes 4810d 19h /xgate/trunk/bench/verilog/tst_bench_top.v
82 Added debug module to assist in software debugging. rehayes 5085d 23h /xgate/trunk/bench/verilog/tst_bench_top.v
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5176d 02h /xgate/trunk/bench/verilog/tst_bench_top.v
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5177d 06h /xgate/trunk/bench/verilog/tst_bench_top.v
65 Parameterize delays based on number of RAM wait states. rehayes 5197d 02h /xgate/trunk/bench/verilog/tst_bench_top.v
62 Cleanup implicit wire declarations. rehayes 5207d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
60 Add ability at insert wait states on RAM access rehayes 5214d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5282d 04h /xgate/trunk/bench/verilog/tst_bench_top.v
50 incremental update to match status bit changes rehayes 5298d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5333d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5361d 06h /xgate/trunk/bench/verilog/tst_bench_top.v
21 Added timeout, total error count, and XGCHN test rehayes 5394d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
11 Update with Single Step debuging test rehayes 5408d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5421d 01h /xgate/trunk/bench/verilog/tst_bench_top.v
2 Initial Checkin rehayes 5428d 23h /xgate/trunk/bench/verilog/tst_bench_top.v

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