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[/] [xgate/] [trunk/] [bench/] [verilog] - Rev 100

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Rev Log message Author Age Path
100 Enabled PC underflow test. rehayes 4195d 14h /xgate/trunk/bench/verilog
99 Memory image for testing PC underflow/overflow. rehayes 4195d 14h /xgate/trunk/bench/verilog
95 Covers all 127 interrupts with one service routine. rehayes 4606d 06h /xgate/trunk/bench/verilog
94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4606d 06h /xgate/trunk/bench/verilog
93 Initial revision, memory image for skipjack test. rehayes 4606d 06h /xgate/trunk/bench/verilog
89 Code cleanup. rehayes 4620d 05h /xgate/trunk/bench/verilog
86 Add JTAG test tasks rehayes 4820d 04h /xgate/trunk/bench/verilog
82 Added debug module to assist in software debugging. rehayes 5095d 08h /xgate/trunk/bench/verilog
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5185d 11h /xgate/trunk/bench/verilog
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5186d 15h /xgate/trunk/bench/verilog
65 Parameterize delays based on number of RAM wait states. rehayes 5206d 11h /xgate/trunk/bench/verilog
62 Cleanup implicit wire declarations. rehayes 5216d 10h /xgate/trunk/bench/verilog
60 Add ability at insert wait states on RAM access rehayes 5223d 10h /xgate/trunk/bench/verilog
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5291d 13h /xgate/trunk/bench/verilog
50 incremental update to match status bit changes rehayes 5307d 10h /xgate/trunk/bench/verilog
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5342d 10h /xgate/trunk/bench/verilog
37 RAM model breakout for testbench rehayes 5370d 15h /xgate/trunk/bench/verilog
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5370d 15h /xgate/trunk/bench/verilog
35 Add byte lane select input to all tasks rehayes 5370d 15h /xgate/trunk/bench/verilog
27 Subversion test, no actual code changes rehayes 5395d 08h /xgate/trunk/bench/verilog

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