OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] - Rev 98

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Fixed PC underflow detect error when loading PC at thread startup. rehayes 4217d 11h /xgate/trunk/rtl
97 Fix lint problems, change lowest interrupt vector from 0 to 1.\nDetect program counter underflow/overflow as a software error. rehayes 4236d 23h /xgate/trunk/rtl
96 Fix lint problems, change lowest interrupt vector from 0 to 1. rehayes 4236d 23h /xgate/trunk/rtl
92 Add sync reset to bypass register. rehayes 4628d 02h /xgate/trunk/rtl
89 Code cleanup. rehayes 4642d 01h /xgate/trunk/rtl
88 Updated with complete code rehayes 4715d 10h /xgate/trunk/rtl
87 First pass JTAG TAP, state machine working but needs work to complete reset of TAP. rehayes 4842d 00h /xgate/trunk/rtl
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5202d 07h /xgate/trunk/rtl
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5207d 08h /xgate/trunk/rtl
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5208d 11h /xgate/trunk/rtl
64 Fixed more bugs related to wait states and debug mode. rehayes 5228d 07h /xgate/trunk/rtl
63 Remove historical output ports that are no longer used. rehayes 5238d 07h /xgate/trunk/rtl
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5245d 07h /xgate/trunk/rtl
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5297d 09h /xgate/trunk/rtl
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5313d 10h /xgate/trunk/rtl
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5329d 07h /xgate/trunk/rtl
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5363d 04h /xgate/trunk/rtl
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5363d 04h /xgate/trunk/rtl
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5364d 06h /xgate/trunk/rtl
40 Update for single program counter adder rehayes 5384d 09h /xgate/trunk/rtl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.