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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 98

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Rev Log message Author Age Path
98 Fixed PC underflow detect error when loading PC at thread startup. rehayes 4270d 17h /xgate/trunk/rtl/verilog
97 Fix lint problems, change lowest interrupt vector from 0 to 1.\nDetect program counter underflow/overflow as a software error. rehayes 4290d 05h /xgate/trunk/rtl/verilog
96 Fix lint problems, change lowest interrupt vector from 0 to 1. rehayes 4290d 05h /xgate/trunk/rtl/verilog
92 Add sync reset to bypass register. rehayes 4681d 08h /xgate/trunk/rtl/verilog
89 Code cleanup. rehayes 4695d 07h /xgate/trunk/rtl/verilog
88 Updated with complete code rehayes 4768d 16h /xgate/trunk/rtl/verilog
87 First pass JTAG TAP, state machine working but needs work to complete reset of TAP. rehayes 4895d 06h /xgate/trunk/rtl/verilog
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5255d 13h /xgate/trunk/rtl/verilog
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5260d 14h /xgate/trunk/rtl/verilog
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5261d 17h /xgate/trunk/rtl/verilog
64 Fixed more bugs related to wait states and debug mode. rehayes 5281d 13h /xgate/trunk/rtl/verilog
63 Remove historical output ports that are no longer used. rehayes 5291d 12h /xgate/trunk/rtl/verilog
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5298d 12h /xgate/trunk/rtl/verilog
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5350d 15h /xgate/trunk/rtl/verilog
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5366d 16h /xgate/trunk/rtl/verilog
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5382d 13h /xgate/trunk/rtl/verilog
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5416d 10h /xgate/trunk/rtl/verilog
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5416d 10h /xgate/trunk/rtl/verilog
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5417d 12h /xgate/trunk/rtl/verilog
40 Update for single program counter adder rehayes 5437d 15h /xgate/trunk/rtl/verilog

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