OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 96

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 Fix lint problems, change lowest interrupt vector from 0 to 1. rehayes 4186d 13h /xgate/trunk/rtl/verilog/xgate_regs.v
92 Add sync reset to bypass register. rehayes 4577d 16h /xgate/trunk/rtl/verilog/xgate_regs.v
89 Code cleanup. rehayes 4591d 15h /xgate/trunk/rtl/verilog/xgate_regs.v
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5156d 22h /xgate/trunk/rtl/verilog/xgate_regs.v
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5158d 01h /xgate/trunk/rtl/verilog/xgate_regs.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5263d 00h /xgate/trunk/rtl/verilog/xgate_regs.v
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5312d 18h /xgate/trunk/rtl/verilog/xgate_regs.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5313d 20h /xgate/trunk/rtl/verilog/xgate_regs.v
24 Delete unused inputs rehayes 5368d 23h /xgate/trunk/rtl/verilog/xgate_regs.v
15 Fix R1 load at boot up, add debug features rehayes 5387d 18h /xgate/trunk/rtl/verilog/xgate_regs.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5388d 21h /xgate/trunk/rtl/verilog/xgate_regs.v
2 Initial Checkin rehayes 5409d 18h /xgate/trunk/rtl/verilog/xgate_regs.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.