URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 41

Rev	Log message	Author	Age	Path
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5360d 15h	/xgate/trunk/rtl/verilog/xgate_regs.v
24	Delete unused inputs	rehayes	5415d 17h	/xgate/trunk/rtl/verilog/xgate_regs.v
15	Fix R1 load at boot up, add debug features	rehayes	5434d 13h	/xgate/trunk/rtl/verilog/xgate_regs.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5435d 15h	/xgate/trunk/rtl/verilog/xgate_regs.v
2	Initial Checkin	rehayes	5456d 13h	/xgate/trunk/rtl/verilog/xgate_regs.v