URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Rev 53

Rev	Log message	Author	Age	Path
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5274d 11h	/xgate/trunk/rtl/verilog/xgate_regs.v
42	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5324d 05h	/xgate/trunk/rtl/verilog/xgate_regs.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5325d 07h	/xgate/trunk/rtl/verilog/xgate_regs.v
24	Delete unused inputs	rehayes	5380d 10h	/xgate/trunk/rtl/verilog/xgate_regs.v
15	Fix R1 load at boot up, add debug features	rehayes	5399d 05h	/xgate/trunk/rtl/verilog/xgate_regs.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5400d 07h	/xgate/trunk/rtl/verilog/xgate_regs.v
2	Initial Checkin	rehayes	5421d 05h	/xgate/trunk/rtl/verilog/xgate_regs.v