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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 64

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64 Fixed more bugs related to wait states and debug mode. rehayes 5179d 03h /xgate/trunk/rtl/verilog/xgate_risc.v
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5196d 02h /xgate/trunk/rtl/verilog/xgate_risc.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5264d 06h /xgate/trunk/rtl/verilog/xgate_risc.v
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5280d 03h /xgate/trunk/rtl/verilog/xgate_risc.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5315d 02h /xgate/trunk/rtl/verilog/xgate_risc.v
40 Update for single program counter adder rehayes 5335d 05h /xgate/trunk/rtl/verilog/xgate_risc.v
34 minor changes related to wishbone master interface rehayes 5343d 07h /xgate/trunk/rtl/verilog/xgate_risc.v
31 Cleanup for MAX_CHANNEL bus rehayes 5355d 02h /xgate/trunk/rtl/verilog/xgate_risc.v
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5370d 03h /xgate/trunk/rtl/verilog/xgate_risc.v
17 Additions for XGCHID debug commands rehayes 5376d 02h /xgate/trunk/rtl/verilog/xgate_risc.v
15 Fix R1 load at boot up, add debug features rehayes 5389d 00h /xgate/trunk/rtl/verilog/xgate_risc.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5390d 02h /xgate/trunk/rtl/verilog/xgate_risc.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5403d 02h /xgate/trunk/rtl/verilog/xgate_risc.v
2 Initial Checkin rehayes 5411d 00h /xgate/trunk/rtl/verilog/xgate_risc.v

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