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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Rev 89

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Rev Log message Author Age Path
89 Code cleanup. rehayes 4587d 01h /xgate/trunk/rtl/verilog/xgate_risc.v
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5147d 07h /xgate/trunk/rtl/verilog/xgate_risc.v
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5152d 08h /xgate/trunk/rtl/verilog/xgate_risc.v
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5153d 11h /xgate/trunk/rtl/verilog/xgate_risc.v
64 Fixed more bugs related to wait states and debug mode. rehayes 5173d 07h /xgate/trunk/rtl/verilog/xgate_risc.v
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5190d 06h /xgate/trunk/rtl/verilog/xgate_risc.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5258d 10h /xgate/trunk/rtl/verilog/xgate_risc.v
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5274d 07h /xgate/trunk/rtl/verilog/xgate_risc.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5309d 06h /xgate/trunk/rtl/verilog/xgate_risc.v
40 Update for single program counter adder rehayes 5329d 09h /xgate/trunk/rtl/verilog/xgate_risc.v
34 minor changes related to wishbone master interface rehayes 5337d 11h /xgate/trunk/rtl/verilog/xgate_risc.v
31 Cleanup for MAX_CHANNEL bus rehayes 5349d 06h /xgate/trunk/rtl/verilog/xgate_risc.v
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5364d 08h /xgate/trunk/rtl/verilog/xgate_risc.v
17 Additions for XGCHID debug commands rehayes 5370d 06h /xgate/trunk/rtl/verilog/xgate_risc.v
15 Fix R1 load at boot up, add debug features rehayes 5383d 04h /xgate/trunk/rtl/verilog/xgate_risc.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5384d 07h /xgate/trunk/rtl/verilog/xgate_risc.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5397d 07h /xgate/trunk/rtl/verilog/xgate_risc.v
2 Initial Checkin rehayes 5405d 04h /xgate/trunk/rtl/verilog/xgate_risc.v

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