URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Rev 43

Rev	Log message	Author	Age	Path
43	Update for single program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5322d 04h	/xgate/trunk/rtl/verilog/xgate_top.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5323d 07h	/xgate/trunk/rtl/verilog/xgate_top.v
34	minor changes related to wishbone master interface	rehayes	5351d 12h	/xgate/trunk/rtl/verilog/xgate_top.v
30	Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus	rehayes	5363d 07h	/xgate/trunk/rtl/verilog/xgate_top.v
25	Fix connected net name	rehayes	5378d 08h	/xgate/trunk/rtl/verilog/xgate_top.v
17	Additions for XGCHID debug commands	rehayes	5384d 07h	/xgate/trunk/rtl/verilog/xgate_top.v
15	Fix R1 load at boot up, add debug features	rehayes	5397d 05h	/xgate/trunk/rtl/verilog/xgate_top.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5398d 07h	/xgate/trunk/rtl/verilog/xgate_top.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5411d 07h	/xgate/trunk/rtl/verilog/xgate_top.v
2	Initial Checkin	rehayes	5419d 05h	/xgate/trunk/rtl/verilog/xgate_top.v