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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Rev 63

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Rev Log message Author Age Path
63 Remove historical output ports that are no longer used. rehayes 5199d 18h /xgate/trunk/rtl/verilog/xgate_top.v
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5274d 21h /xgate/trunk/rtl/verilog/xgate_top.v
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5324d 16h /xgate/trunk/rtl/verilog/xgate_top.v
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5325d 18h /xgate/trunk/rtl/verilog/xgate_top.v
34 minor changes related to wishbone master interface rehayes 5353d 23h /xgate/trunk/rtl/verilog/xgate_top.v
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5365d 18h /xgate/trunk/rtl/verilog/xgate_top.v
25 Fix connected net name rehayes 5380d 19h /xgate/trunk/rtl/verilog/xgate_top.v
17 Additions for XGCHID debug commands rehayes 5386d 18h /xgate/trunk/rtl/verilog/xgate_top.v
15 Fix R1 load at boot up, add debug features rehayes 5399d 16h /xgate/trunk/rtl/verilog/xgate_top.v
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5400d 18h /xgate/trunk/rtl/verilog/xgate_top.v
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5413d 18h /xgate/trunk/rtl/verilog/xgate_top.v
2 Initial Checkin rehayes 5421d 16h /xgate/trunk/rtl/verilog/xgate_top.v

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