URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Rev 96

Rev	Log message	Author	Age	Path
96	Fix lint problems, change lowest interrupt vector from 0 to 1.	rehayes	4190d 04h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
89	Code cleanup.	rehayes	4595d 06h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5266d 15h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
34	minor changes related to wishbone master interface	rehayes	5345d 16h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
29	Added some constant assigments, still needs more work to complete	rehayes	5357d 12h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v
12	Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits	rehayes	5392d 12h	/xgate/trunk/rtl/verilog/xgate_wbm_bus.v