URL https://opencores.org/ocsvn/xgate/xgate/trunk

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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Rev 96

Rev	Log message	Author	Age	Path
96	Fix lint problems, change lowest interrupt vector from 0 to 1.	rehayes	4186d 12h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
89	Code cleanup.	rehayes	4591d 14h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
72	Code cleanup, eliminated index 0 of input and output interrupts.	rehayes	5156d 21h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
67	Added irq bypass function and controll registers. Made lowest interrupt index highest priority.	rehayes	5158d 00h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
57	Traded 16 data registers for 5 address regester when wait states are enabled.	rehayes	5246d 22h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
53	Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.	rehayes	5262d 23h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
41	Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection	rehayes	5313d 19h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
17	Additions for XGCHID debug commands	rehayes	5374d 19h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
5	Update for memory wait states, testbench and instruction decoder simplified for synthesis	rehayes	5401d 19h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v
2	Initial Checkin	rehayes	5409d 17h	/xgate/trunk/rtl/verilog/xgate_wbs_bus.v