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[/] [xgate/] [trunk/] [rtl] - Rev 59

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Rev Log message Author Age Path
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5242d 06h /xgate/trunk/rtl
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5294d 09h /xgate/trunk/rtl
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5310d 10h /xgate/trunk/rtl
47 Fix status bit error in ADC and SBC instruction, fix error in thread startup. rehayes 5326d 07h /xgate/trunk/rtl
43 Update for single program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5360d 04h /xgate/trunk/rtl
42 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5360d 04h /xgate/trunk/rtl
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5361d 06h /xgate/trunk/rtl
40 Update for single program counter adder rehayes 5381d 09h /xgate/trunk/rtl
34 minor changes related to wishbone master interface rehayes 5389d 11h /xgate/trunk/rtl
31 Cleanup for MAX_CHANNEL bus rehayes 5401d 06h /xgate/trunk/rtl
30 Added pins debud_mode_i and secure_mode_i. Cleanup for xgif bus rehayes 5401d 06h /xgate/trunk/rtl
29 Added some constant assigments, still needs more work to complete rehayes 5401d 06h /xgate/trunk/rtl
28 Added comment line rehayes 5401d 06h /xgate/trunk/rtl
26 Add synopsys commands, add else defaults for semphore state machine. rehayes 5416d 08h /xgate/trunk/rtl
25 Fix connected net name rehayes 5416d 08h /xgate/trunk/rtl
24 Delete unused inputs rehayes 5416d 09h /xgate/trunk/rtl
17 Additions for XGCHID debug commands rehayes 5422d 06h /xgate/trunk/rtl
15 Fix R1 load at boot up, add debug features rehayes 5435d 04h /xgate/trunk/rtl
12 Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits rehayes 5436d 07h /xgate/trunk/rtl
5 Update for memory wait states, testbench and instruction decoder simplified for synthesis rehayes 5449d 07h /xgate/trunk/rtl

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