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[/] [xgate] - Rev 71

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Rev Log message Author Age Path
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5178d 15h /xgate
70 Updated with interrupt bypass controll registers. rehayes 5178d 15h /xgate
69 New test to verify irq interrupt priority encoder. rehayes 5178d 15h /xgate
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5178d 16h /xgate
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5178d 16h /xgate
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5198d 11h /xgate
65 Parameterize delays based on number of RAM wait states. rehayes 5198d 11h /xgate
64 Fixed more bugs related to wait states and debug mode. rehayes 5198d 11h /xgate
63 Remove historical output ports that are no longer used. rehayes 5208d 11h /xgate
62 Cleanup implicit wire declarations. rehayes 5208d 11h /xgate
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5215d 10h /xgate
60 Add ability at insert wait states on RAM access rehayes 5215d 11h /xgate
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5215d 11h /xgate
58 WISHBONE Bus update. rehayes 5267d 10h /xgate
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5267d 13h /xgate
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5283d 14h /xgate
55 Minor change to instruction set details. rehayes 5283d 14h /xgate
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 14h /xgate
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5283d 14h /xgate
52 Minor changes to aide waveform debug rehayes 5283d 14h /xgate

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