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[/] [xgate] - Rev 73

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73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5296d 07h /xgate
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5296d 07h /xgate
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5297d 10h /xgate
70 Updated with interrupt bypass controll registers. rehayes 5297d 10h /xgate
69 New test to verify irq interrupt priority encoder. rehayes 5297d 10h /xgate
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5297d 10h /xgate
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5297d 10h /xgate
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5317d 06h /xgate
65 Parameterize delays based on number of RAM wait states. rehayes 5317d 06h /xgate
64 Fixed more bugs related to wait states and debug mode. rehayes 5317d 06h /xgate
63 Remove historical output ports that are no longer used. rehayes 5327d 06h /xgate
62 Cleanup implicit wire declarations. rehayes 5327d 06h /xgate
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5334d 05h /xgate
60 Add ability at insert wait states on RAM access rehayes 5334d 06h /xgate
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5334d 06h /xgate
58 WISHBONE Bus update. rehayes 5386d 05h /xgate
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5386d 08h /xgate
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5402d 09h /xgate
55 Minor change to instruction set details. rehayes 5402d 09h /xgate
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5402d 09h /xgate

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