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Rev Log message Author Age Path
77 Documentation update rehayes 5178d 19h /xgate
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5201d 20h /xgate
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5201d 21h /xgate
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5206d 22h /xgate
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5206d 22h /xgate
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5206d 22h /xgate
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5208d 00h /xgate
70 Updated with interrupt bypass controll registers. rehayes 5208d 00h /xgate
69 New test to verify irq interrupt priority encoder. rehayes 5208d 01h /xgate
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5208d 01h /xgate
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5208d 01h /xgate
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5227d 21h /xgate
65 Parameterize delays based on number of RAM wait states. rehayes 5227d 21h /xgate
64 Fixed more bugs related to wait states and debug mode. rehayes 5227d 21h /xgate
63 Remove historical output ports that are no longer used. rehayes 5237d 21h /xgate
62 Cleanup implicit wire declarations. rehayes 5237d 21h /xgate
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5244d 20h /xgate
60 Add ability at insert wait states on RAM access rehayes 5244d 20h /xgate
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5244d 20h /xgate
58 WISHBONE Bus update. rehayes 5296d 20h /xgate

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