URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_medium.v] - Rev 22

Rev	Log message	Author	Age	Path
22	Added prototype system verilog testbench	antanguay	4363d 04h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4363d 04h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
20	Updates for Xilinx synthesis	antanguay	4652d 23h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
7	New directory structure.	root	5717d 16h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
2	Initial revision	antanguay	6000d 03h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v