URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_medium.v] - Rev 25

Rev	Log message	Author	Age	Path
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4212d 02h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
22	Added prototype system verilog testbench	antanguay	4214d 06h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4214d 07h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
20	Updates for Xilinx synthesis	antanguay	4504d 01h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
7	New directory structure.	root	5568d 18h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v
2	Initial revision	antanguay	5851d 05h	/xge_mac/trunk/rtl/verilog/generic_mem_medium.v