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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [rx_enqueue.v] - Rev 21

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Rev Log message Author Age Path
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4360d 01h /xge_mac/trunk/rtl/verilog/rx_enqueue.v
12 Change interface to big endian, added serdes examples to testbench antanguay 5436d 03h /xge_mac/trunk/rtl/verilog/rx_enqueue.v
7 New directory structure. root 5714d 12h /xge_mac/trunk/rtl/verilog/rx_enqueue.v
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5990d 20h /xge_mac/trunk/rtl/verilog/rx_enqueue.v
2 Initial revision antanguay 5997d 00h /xge_mac/trunk/rtl/verilog/rx_enqueue.v

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