URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_dequeue.v] - Rev 24

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4207d 10h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
23	Adding basic packet stats	antanguay	4207d 16h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4209d 13h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
20	Updates for Xilinx synthesis	antanguay	4499d 08h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5285d 15h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
10	Added details to spec	antanguay	5489d 07h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
7	New directory structure.	root	5564d 00h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5840d 08h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v
2	Initial revision	antanguay	5846d 12h	/xge_mac/trunk/rtl/verilog/tx_dequeue.v