URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [wishbone_if.v] - Rev 28

Rev	Log message	Author	Age	Path
28	Adding parameter for max frame size	antanguay	4482d 14h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
27	Fix octets stats on barrel shift transitions	antanguay	4531d 14h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
24	Use FIFO's for statistics clock domain crossing	antanguay	4537d 17h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
23	Adding basic packet stats	antanguay	4537d 23h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
20	Updates for Xilinx synthesis	antanguay	4829d 14h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
12	Change interface to big endian, added serdes examples to testbench	antanguay	5615d 22h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
7	New directory structure.	root	5894d 07h	/xge_mac/trunk/rtl/verilog/wishbone_if.v
2	Initial revision	antanguay	6176d 19h	/xge_mac/trunk/rtl/verilog/wishbone_if.v