URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk] - Rev 24

Rev	Log message	Author	Age	Path
24	Use FIFO's for statistics clock domain crossing	antanguay	4241d 01h	/xge_mac/trunk
23	Adding basic packet stats	antanguay	4241d 07h	/xge_mac/trunk
22	Added prototype system verilog testbench	antanguay	4243d 04h	/xge_mac/trunk
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4243d 04h	/xge_mac/trunk
20	Updates for Xilinx synthesis	antanguay	4532d 23h	/xge_mac/trunk
19	Updates for 32/64 bit systems	antanguay	4708d 00h	/xge_mac/trunk
18	Updates for linux 32-bit	antanguay	4708d 20h	/xge_mac/trunk
17	Fixed deprecated SystemC warnings	antanguay	4711d 04h	/xge_mac/trunk
16	Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim	antanguay	4711d 11h	/xge_mac/trunk
15	Updated for Verilator 3.813	antanguay	4730d 11h	/xge_mac/trunk
14	Change interface to big endian, added serdes examples to testbench	antanguay	5319d 05h	/xge_mac/trunk
13	Change interface to big endian, added serdes examples to testbench	antanguay	5319d 06h	/xge_mac/trunk
12	Change interface to big endian, added serdes examples to testbench	antanguay	5319d 06h	/xge_mac/trunk
11	Fixed clock crossing	antanguay	5425d 04h	/xge_mac/trunk
10	Added details to spec	antanguay	5522d 23h	/xge_mac/trunk
7	New directory structure.	root	5597d 16h	/xge_mac/trunk
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5873d 23h	/trunk
5	Fixed compilation	antanguay	5880d 00h	/trunk
4	Created	antanguay	5880d 02h	/trunk
2	Initial revision	antanguay	5880d 03h	/trunk