URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [tb_generic_ram.vhdl] - Rev 26

Rev	Log message	Author	Age	Path
26	Added test data for 32k memory. Added GTKW configuration file.	lcdsgmtr	3426d 06h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
25	Problem with memory: created conditional generate based upon data width instead of address width.	lcdsgmtr	3426d 06h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
23	Currently moved test bench to 10 bit address. Created spreadsheet for filling memory with random data. When testing, memory is apparently not initialised.	lcdsgmtr	3426d 06h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
20	Update RAM package to allow for 15-bit address. Update test bench to use address width parameter.	lcdsgmtr	3426d 06h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
17	Moving the generic block ram component piece by piece to a better implementation.	lcdsgmtr	3426d 06h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
5	Re-organisation of repository.	lcdsgmtr	3560d 06h	/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl
2	First checkin to make sure that the project does not get stale.	lcdsgmtr	3682d 07h	/xucpu/trunk/VHDL/blockram/tb_generic_ram.vhdl